Sundance SMT310 v.1.6 Manual de usuario

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 SMT310 User Manual V1.6

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 3 Setting Up the SMT310 The SMT310 should be set up in

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 4 Memory Map All address information is given in bytes :

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 4.3 Memory Space Assignments(BAR2) Address Descripti

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 5 DSP Resource Memory Map The Master module on the SMT3

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 6 Shared Memory Resource The shared memory on the SMT3

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 7 Sundance Digital Bus (SDB) A growing number of Sundan

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 8 ComPorts The SMT310 gives access to all six TIM site C

Page 17 of 50 SMT310 User Manual V1.6 Table 6 : ComPort configuration register The table below illustrates the different setting of the register.

Page 18 of 50 SMT310 User Manual V1.6 allows cable less connection between the TIM site and the buffer. There is also a 14-way surface-mount FMS c

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 9 ComPort to PCI Interface The ComPort interface is mem

Page 2 of 50 SMT310 User Manual V1.6 Revision History Date Comments Engineer Version 11/04/00 Initial SMT310 Draft AJP 0.5 21/08/00 ComPort

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 9.3 Status Register (Offset 0x14, BAR1 , Read-Only)

Page 21 of 50 SMT310 User Manual V1.6 CONFIG_L Reflects the state of the TIMs’ CONFIG signal. Active low. Table 9 : Status Register INTD is the i

Page 22 of 50 SMT310 User Manual V1.6 Table 10 : Interrupt Control Register The JTAG controller which generates TBC INT must be cleared of all int

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 10 JTAG Controller The SMT310 has an on board Test Bus C

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 11 Using the SMT310 External/Internal JTAG with TI Tools

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 12 Firmware Upgrades Much of the SMT310’s control interf

Page 26 of 50 SMT310 User Manual V1.6 1 5 6 342 Figure 3 : JTAG header pin numbers Pin Number Function 1 Vcc (5v) 2 Gnd 3 TCK 4 TDO 5 TDI

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 13 Global/Local Bus Transfers, DSP <-> PCI. The

Page 28 of 50 SMT310 User Manual V1.6 The mailbox registers are accessed from the DSP through the Local-to-Internal Register (LB_IO_BASE) aperture

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 13.3 DSP To Local Aperture 0 control and Accessing Th

Page 3 of 50 SMT310 User Manual V1.6 Table of Contents 1 Introduction ...

Page 30 of 50 SMT310 User Manual V1.6 i.e. 0xFE12 3000 Receive Target address via Com-Port Link WritePCIRegisters((unsigned int)LB_

Page 31 of 50 SMT310 User Manual V1.6 13.3.1 Global bus access protocol In Figure 6, the WritePCIApperture function calls a function C6xGlobalWri

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 A0..A30 DSP’s global Bus address lines D0..D31 DSP’s glo

Page 33 of 50 SMT310 User Manual V1.6 full, the arbitration logic de-asserts the RDY1 signal to indicate a hold-off state. Once the data has been

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 14 Interrupts 14.1 SMT310-To-PCI Interrupts TBC INTINTA

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 14.2 PCI-To-SMT310 Interrupts TIMIIOF0TIMIIOF1TIMIIOF2

Page 36 of 50 SMT310 User Manual V1.6 26 - Reserved 25 DMA1 DMA Channel 1 interrupt enable 24 DMA0 DMA Channel 0 interrupt enable 23-22 MODE_

Page 37 of 50 SMT310 User Manual V1.6 5 INTB_TO_LB 1=INTB will request LICU interrupts when the input is active 0=INTB will never request LICU i

Page 38 of 50 SMT310 User Manual V1.6 occurred on INTC 13 INTB_TO_D INTD output from INTB input: when set (1) an interrupt has occurred on INTB

Page 39 of 50 SMT310 User Manual V1.6 1 DMA1 DMA channel 1 interrupt enable 0 DMA0 DMA channel 0 interrupt enable Table 14 : Local Bus Interr

Page 4 of 50 SMT310 User Manual V1.6 14.3.6 Local Bus Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD4, BAR0 Read 0xD6, BAR0) ...

Page 40 of 50 SMT310 User Manual V1.6 3 EN3 Same as above for mailbox 3 2 EN2 Same as above for mailbox 2 1 EN1 Same as above for mailbox 1

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 14.3.7 Mailbox Write/Read Interrupt Status Register(Offs

Page 42 of 50 SMT310 User Manual V1.6 10 - Reserved 9 - Reserved 8 - Reserved 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 Mailbox Write/Read Interrupt Status Register(Offset: Wri

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 15 Performance Figures Following are the performance fig

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 16 Mechanical Dimensions The board size is 108 mm by 175

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 18 Cables and Connectors 18.1 SDB No SDB cables are supp

Page 47 of 50 SMT310 User Manual V1.6 This cable has 13 individual pairs, with an overall shield, and an outer diameter of 7mm. Cable length shoul

Page 48 of 50 SMT310 User Manual V1.6 When the buffered ComPort is reset to input, pins 1 and 23 are always driven and pins 3 and 25 are always re

Page 49 of 50 SMT310 User Manual V1.6 16 CONFIG OPEN COLL Global open collector C4x CONFIG 17 EMU0 IN Buffered EMU0 output 18 EMU1 IN Buf

Page 5 of 50 SMT310 User Manual V1.6 Table of Tables Table 1 : Table of Abbreviations ...

Page 50 of 50 SMT310 User Manual V1.6 19 Where’s that Jumper? Below is a diagram to help locate the jumpers: J21 JTAG programming header

Page 6 of 50 SMT310 User Manual V1.6 Table of Figures Figure 1: ComPort connection diagram ...

Page 7 of 50 SMT310 User Manual V1.6 Table Of Abbreviations BAR Base Address Region DMA Direct Memory Access EPLD Electrically Programmable Lo

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 1 Introduction The SMT310 is a single site module carrie

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 2 Functional Description The PCI interface connects to a