Sundance SMT950 Manual de usuario

SMT950 User Manual

Version 2.0 Page 10 of 52 SMT950 User Manual Possible applications The SMT950 can be used for the following application (this non-exhaustive list

Version 2.0 Page 11 of 52 SMT950 User Manual Functional Description In this part, we will see the general block diagram and some comments on some

Version 2.0 Page 12 of 52 SMT950 User Manual the inter-module connector (SLB – Sundance LVDS Bus, used in this case as ‘single-ended’). DAC: Digi

Version 2.0 Page 13 of 52 SMT950 User Manual ADC Channels. ADC Main Characteristics. The main characteristics of the SMT950 ADCs are gathered into

Version 2.0 Page 14 of 52 SMT950 User Manual Figure 4 - ADC Input Stage. The SMT950 can also receive an DC-coupling input stage on request as sho

Version 2.0 Page 15 of 52 SMT950 User Manual Clock Structure There is one integrated clock generator on the module (AD9510 – Analog Devices). The u

Version 2.0 Page 16 of 52 SMT950 User Manual Dual-Channel DAC. DAC Main characteristics. The main characteristics of the SMT950 DAC are gathered

Version 2.0 Page 17 of 52 SMT950 User Manual Jumper J1 disables (position 1-2; also called External Clock Mode) or enables (position2-3; also calle

Version 2.0 Page 18 of 52 SMT950 User Manual Figure 8 - Clock Structure. ADCs can both receive the same clock or the fraction of the CDCM7005 inp

Version 2.0 Page 19 of 52 SMT950 User Manual The same applies to the DAC, with a maximum sampling frequency for clk1 of 250MHz and for clk2 of 500M

Version 2.0 Page 2 of 52 SMT950 User Manual Revision History Changes Made Issue Initials 02/09/08 Original Document based on SMT350 User Manual

Version 2.0 Page 20 of 52 SMT950 User Manual Output Voltage Level 0-2.4 Volts fixed amplitude Output Format LVTTL External Trigger Inputs Input Vol

Version 2.0 Page 21 of 52 SMT950 User Manual Sundance defines these two connectors as the Sundance LVDS Bus (SLB). It has originally been made for

Version 2.0 Page 22 of 52 SMT950 User Manual The male power connector is located on the mezzanine card. The Samtec Part Number for this connector i

Version 2.0 Page 23 of 52 SMT950 User Manual 16 DGND Digital Ground 17 D+12V0 Digital +12.0 Volts – not used on the SMT950 18 DGND Digital Grou

Version 2.0 Page 24 of 52 SMT950 User Manual Bank A Bank B Bank C 1 3 5 7 41 43 81 83 2

Version 2.0 Page 25 of 52 SMT950 User Manual Bank A Bank B Bank C 1 3 5 7 41 43 81 83 2

Version 2.0 Page 26 of 52 SMT950 User Manual 77 MspTms Reserved 78 MspTdi Reserved. 79 Msptdo Reserved 80 MspnTrst Reserved Figure 14 – Daug

Version 2.0 Page 27 of 52 SMT950 User Manual Bank A Bank B Bank C 1 3 5 7 41 43 81 83 2

Version 2.0 Page 28 of 52 SMT950 User Manual Control Register Settings The Control Registers control the complete functionality of the SMT950. The

Version 2.0 Page 29 of 52 SMT950 User Manual Memory Map The write packets must contain the address where the data must be written to and the read p

Version 2.0 Page 3 of 52 SMT950 User Manual Table of Contents Physical Properties...

Version 2.0 Page 30 of 52 SMT950 User Manual 0x24 DDS Register 4 – Step Phase Increment LSB Read-back (FPGA Register) DDS Register 4. 0x25 DDS Reg

Version 2.0 Page 31 of 52 SMT950 User Manual 2 10 DAC PHSTR line is driven Low. 3 11 Normal Operation – DAC PHSTR is Tri-Stated. Setting Bit 5

Version 2.0 Page 32 of 52 SMT950 User Manual ADCA Register 1 – 0x3. For more details, refer to ADS5500 datasheet. ADCA Register 1 – 0x3 Byte Bit

Version 2.0 Page 33 of 52 SMT950 User Manual ADCB Register 0 – 0x5 Setting Bit 1 Description 0 0 PLL OFF – for sampling frequencies between 10

Version 2.0 Page 34 of 52 SMT950 User Manual DAC Register 0 – 0x8. For more details, refer to DAC5686 datasheet. DAC Register 0 – 0x8 Byte Bit 7

Version 2.0 Page 35 of 52 SMT950 User Manual DAC Register 4 – 0xC. For more details, refer to DAC5686 datasheet. DAC Register 4 – 0xC Byte Bit 7

Version 2.0 Page 36 of 52 SMT950 User Manual CDCM7005 Register 0 – 0x10. For more details, refer to CDCM7005 datasheet. CDCM7005 Register 0 – 0x1

Version 2.0 Page 37 of 52 SMT950 User Manual CDCM7005 Register 4 – 0x14. For more details, refer to CDCM7005 datasheet. CDCM7005 Register 4 – 0x1

Version 2.0 Page 38 of 52 SMT950 User Manual Main Module Temperature (not implemented) – 0x18 Main Module Temperature – 0x18 Byte Bit 7 Bit 6

Version 2.0 Page 39 of 52 SMT950 User Manual 0 0 Polarity DAC Trigger signal selected – Non-Inverting. 1 1 Polarity DAC Trigger signal selected –

Version 2.0 Page 4 of 52 SMT950 User Manual ADCA Register 2 – 0x4. ...

Version 2.0 Page 40 of 52 SMT950 User Manual Updates, Read-back and Firmware Version Registers – 0x1D The Update bit activates the corresponding Se

Version 2.0 Page 41 of 52 SMT950 User Manual DDS Register 1 – Start Phase Increment MSB - 0x21 DDS Register 1 – 0x21 Byte Bit 7 Bit 6 Bit 5

Version 2.0 Page 42 of 52 SMT950 User Manual The Stop Phase Increment value is coded on 32 bits (DDS Data registers 0x22 and 0x23). Each value corr

Version 2.0 Page 43 of 52 SMT950 User Manual DAC (DAC5687) Register 0x0 – 0x30 For more details, refer to DAC5687 datasheet. DAC (DAC5687) Regist

Version 2.0 Page 44 of 52 SMT950 User Manual DAC (DAC5687) Register 0x4 – 0x34 For more details, refer to DAC5687 datasheet. DAC (DAC5687) Regist

Version 2.0 Page 45 of 52 SMT950 User Manual DAC (DAC5687) Register 0x8 – 0x38 For more details, refer to DAC5687 datasheet. DAC (DAC5687) Regist

Version 2.0 Page 46 of 52 SMT950 User Manual DAC (DAC5687) Register 0xC – 0x3C For more details, refer to DAC5687 datasheet. DAC (DAC5687) Regist

Version 2.0 Page 47 of 52 SMT950 User Manual FPGA Design The following block diagram shows how the default FPGA design is structured: SLBSMT368 V

Version 2.0 Page 48 of 52 SMT950 User Manual Block of registers This implements what has previously been described in this document. Space availab

Version 2.0 Page 49 of 52 SMT950 User Manual PCB Layout The following figures show the top and bottom view of the main module, the top view of th

Version 2.0 Page 5 of 52 SMT950 User Manual DAC (DAC5687) Register 0x1 – 0x31... 43 D

Version 2.0 Page 50 of 52 SMT950 User Manual Figure 22 - Daughter Module Component Side. Figure 23 - Daughter Module Solder Side.

Version 2.0 Page 51 of 52 SMT950 User Manual Connectors Description The following table gathers all connectors on the board and describes their fu

Version 2.0 Page 52 of 52 SMT950 User Manual Location on the board Figure 24 - Connectors Location.

Version 2.0 Page 6 of 52 SMT950 User Manual Figure 8 - Clock Structure. ...

Version 2.0 Page 7 of 52 SMT950 User Manual Physical Properties Dimensions 63.5mm x 106.7mm x 18mm Weight 35 grams Supply Voltages Supply

Version 2.0 Page 8 of 52 SMT950 User Manual Precautions In order to guarantee that Sundance’s boards function correctly and to protect the module f

Version 2.0 Page 9 of 52 SMT950 User Manual Introduction Overview The SMT950 is a single width expansion TIM that plugs onto the SLB base module SM