Sundance FC202 FPGA Manual de usuario descargar pdf (Pagina 17)

Sundance Digital Signal Processing Inc. Rev1.0

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..\fc202_ea1\simulink\fc202_fpga\

Figure 5 - In-Phase and Quadrature output generated by DSP model

The PARS generated test bench “Subsystem2_TestBench.mdl” can be found under

..\fc202_ea1\simulink\fc202_dsp\fc202_dsp_PARS\

Figure 6 below shows the results generated by the actual core executed on an FPGA.

The delay in the In-Phase signal is due to the hardware delay. This cannot be seen in the DSP

model above as the Hilbert transform component is implemented only for the Quadrature

output.

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Sundance FC202 FPGA Manual de usuario Pagina 17