Sundance SMT130 v.1.0 Manual de usuario

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Indice de contenidos

Pagina 1 - User Manual V1.0

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 SMT130 User Manual V1.0

Pagina 2 - Revision History

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 3 Setting Up the SMT130 The SMT130 should be set up in

Pagina 3 - Table of Contents

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 4 Memory Map All address information is given in bytes :

Pagina 4 - Read 0xDA

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 4.3 Memory Space Assignments(BAR2) Address Descripti

Pagina 5 - Table of Tables

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 5 DSP Resource Memory Map The Master module on the SMT1

Pagina 6 - Table of Figures

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 6 Shared Memory Resource There is 1Mbyte of SRAM on th

Pagina 7 - Table Of Abbreviations

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 7 Comports The SMT130 gives access to five of the six TI

Pagina 8 - 1 Introduction

Page 16 of 46 SMT130 User Manual V1.0 8 Comport to PCI Interface The Comport interface is memory mapped to the PCI Bridge as illustrated in tabl

Pagina 9 - 2 Functional Description

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 8.3 Status Register (Offset 0x14, BAR1 , Read-Only)

Pagina 10 - 3 Setting Up the SMT130

Page 18 of 46 SMT130 User Manual V1.0 CONFIG_L Reflects the state of the TIMs’ CONFIG signal. Active low. Table 7 : Status Register INTD is the i

Pagina 11 - 4 Memory Map

Page 19 of 46 SMT130 User Manual V1.0 Table 8 : Interrupt Control Register The JTAG controller which generates TBC INT must be cleared of all inte

Pagina 12

Page 2 of 46 SMT130 User Manual V1.0 Revision History Date Comments Engineer Version 24/05/04 Initial SMT130 Draft TJW 1.0

Pagina 13 - 5 DSP Resource Memory Map

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 9 JTAG Controller The SMT130 has an on board Test Bus Co

Pagina 14 - 6 Shared Memory Resource

Page 21 of 46 SMT130 User Manual V1.0 JTAG chain can be automatically connected through the stack by inserting a JTAG coupling connector. If this

Pagina 15 - 7 Comports

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 10 Using the SMT130 External/Internal JTAG with TI Tools

Pagina 16 - 8 Comport to PCI Interface

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 11 Firmware Upgrades Much of the SMT130’s control interf

Pagina 17 - 0 MASTER IBF OBF

Page 24 of 46 SMT130 User Manual V1.0 Pin Number Function 1 Vcc (5v) 2 Gnd 3 TCK 4 TDO 5 TDI 6 TMS Table 9 : JTAG Header pin function

Pagina 18 - 0x4C, BAR0)

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 12 Global/Local Bus Transfers, DSP <-> PCI. The

Pagina 19

Page 26 of 46 SMT130 User Manual V1.0 The mailbox registers are accessed from the DSP through the Local-to-Internal Register (LB_IO_BASE) aperture

Pagina 20 - 9 JTAG Controller

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 12.3 DSP To Local Aperture 0 control and Accessing Th

Pagina 21

Page 28 of 46 SMT130 User Manual V1.0 Unlock the system register in PCI Bridge #define LB_CFG_SYSTEM (0x78>>

Pagina 22

Page 29 of 46 SMT130 User Manual V1.0 12.3.1 Global bus access protocol In Figure 6, the WritePCIApperture function calls a function C6xGlobalWri

Pagina 23 - 11 Firmware Upgrades

Page 3 of 46 SMT130 User Manual V1.0 Table of Contents 1 Introduction ...

Pagina 24

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 A0..A30 DSP’s global Bus address lines D0..D31 DSP’s glo

Pagina 25

Page 31 of 46 SMT130 User Manual V1.0 full, the arbitration logic de-asserts the RDY1 signal to indicate a hold-off state. Once the data has been

Pagina 26 - SMT130 User Manual V1.0

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 13 Interrupts 13.1 SMT130-To-PCI Interrupts TBC INTINTA

Pagina 27 - function writes data over

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 13.2 PCI-To-SMT130 Interrupts TIMIIOF0TIMIIOF1TIMIIOF2

Pagina 28

Page 34 of 46 SMT130 User Manual V1.0 26 - Reserved 25 DMA1 DMA Channel 1 interrupt enable 24 DMA0 DMA Channel 0 interrupt enable 23-22 MODE_

Pagina 29 - STAT0..3

Page 35 of 46 SMT130 User Manual V1.0 5 INTB_TO_LB 1=INTB will request LICU interrupts when the input is active 0=INTB will never request LICU i

Pagina 30

Page 36 of 46 SMT130 User Manual V1.0 occurred on INTC 13 INTB_TO_D INTD output from INTB input: when set (1) an interrupt has occurred on INTB

Pagina 31

Page 37 of 46 SMT130 User Manual V1.0 1 DMA1 DMA channel 1 interrupt enable 0 DMA0 DMA channel 0 interrupt enable Table 12 : Local Bus Interr

Pagina 32 - 13 Interrupts

Page 38 of 46 SMT130 User Manual V1.0 3 EN3 Same as above for mailbox 3 2 EN2 Same as above for mailbox 2 1 EN1 Same as above for mailbox 1

Pagina 33 - Control Register (Offset

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 13.3.7 Mailbox Write/Read Interrupt Status Register(Offs

Pagina 34

Page 4 of 46 SMT130 User Manual V1.0 13.3.7 Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0 Read 0xDA, BAR0) 39 13.3.8 INT

Pagina 35 - Bits Name Description

Page 40 of 46 SMT130 User Manual V1.0 10 - Reserved 9 - Reserved 8 - Reserved 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2

Pagina 36 - Bits Name Description

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 Mailbox Write/Read Interrupt Status Register(Offset: Wri

Pagina 37 - BAR0 Read 0xD2, BAR0)

Page 42 of 46 SMT130 User Manual V1.0 14 Stand-alone mode For the SMT130 to operate in stand-alone mode Jumper J9 (Figure 8 : Jumper Finder Diagr

Pagina 38 - 0xD4, BAR0 Read 0xD6, BAR0)

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 15 Performance Figures Following are the performance fig

Pagina 39 - Read 0xDA, BAR0)

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 16 Mechanical Dimensions The SMT130 size is 95.8 mm by 1

Pagina 40 - Table 17 : INTREG Register

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 18 Cables and Connectors 18.1 Comports The cables used w

Pagina 41

Page 46 of 46 SMT130 User Manual V1.0 19 Where’s that Jumper? Below is a diagram to help locate the jumpers: Rotary switch (SW1)_ Comport 4 (J

Pagina 42 - 14 Stand-alone mode

Page 5 of 46 SMT130 User Manual V1.0 Table of Tables Table 1 : Table of Abbreviations ...

Pagina 43 - 15 Performance Figures

Page 6 of 46 SMT130 User Manual V1.0 Table of Figures Figure 1 : TBC Data Routing ...

Pagina 44 - 17 Power consumption

Page 7 of 46 SMT130 User Manual V1.0 Table Of Abbreviations BAR Base Address Region DMA Direct Memory Access EPLD Electrically Programmable Lo

Pagina 45 - 18 Cables and Connectors

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 1 Introduction The SMT130 is a single site module carrie

Pagina 46 - 19 Where’s that Jumper?

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999 2 Functional Description The PCI interface connects to a

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